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| STB80NE03L-06 STB80NE03L-06-1 N-CHANNEL 30V - 0.005 - 80A D2PAK / I2PAK STripFETTM POWER MOSFET TYPE STB80NE03L-06 STB80NE03L-06-1 s s s s VDSS 30 V 30 V RDS(on) < 0.006 < 0.006 ID 80 A 80 A TYPICAL RDS(on) = 0.005 EXCEPTIONAL dv/dt CAPABILITY LOW GATE CHARGE 100C 100% AVALANCHE TESTED 3 1 3 12 DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. D2PAK I2PAK INTERNAL SCHEMATIC DIAGRAM APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING s SOLENOID AND RELAY DRIVERS s MOTOR CONTROL,AUDIO AMPLIFIERS s DC-DC & DC-AC CONVERTERS s AUTOMOTIVE ENVIRONMENT (INJECTION, ABS, AIR-BAG, LAMPDRIVERS, Etc.) s ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM ( ) PTOT dv/dt (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 30 30 20 80 60 320 150 1 7 - 55 to 175 (1) ISD 804A, di/dt 300A/s, VDD V(BR)DSS, T j TJMAX. Unit V V V A A A W W/C V/ns C (q) Pulse width limited by safe operating area February 2003 1/9 STB80NE03L-06 / STB80NE03L-06-1 THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1 62.5 300 C/W C/W C AVALANCHE CHARACTERISTICS Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 15 V) Max Value 80 600 Unit A mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20 V Min. 30 1 10 100 Typ. Max. Unit V A A nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10 V, ID = 40 A VGS = 4.5 V, ID = 40 A Min. 1 Typ. 1.7 0.005 Max. 2.5 0.006 0.008 Unit V DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 40 A VDS = 25V, f = 1 MHz, VGS = 0 Min. 30 Typ. 50 6500 1500 500 Max. Unit S pF pF pF 2/9 STB80NE03L-06 / STB80NE03L-06-1 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 15 V, ID = 40 A RG = 4.7 VGS = 4.5 V (see test circuit, Figure 3) VDD = 24 V, ID = 80A, VGS = 5V Min. Typ. 40 260 95 30 44 Max. 55 350 130 Unit ns ns nC nC nC SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 24 V, ID = 80 A, RG = 4.7, VGS = 5V (see test circuit, Figure 3) Min. Typ. 70 165 250 Max. 95 220 340 Unit ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80 A, VGS = 0 ISD = 80 A, di/dt = 100A/s, VDD = 15 V, Tj = 150C (see test circuit, Figure 5) 75 0.14 4 Test Conditions Min. Typ. Max. 80 320 1.5 Unit A A V ns nC A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedence 3/9 STB80NE03L-06 / STB80NE03L-06-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STB80NE03L-06 / STB80NE03L-06-1 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STB80NE03L-06 / STB80NE03L-06-1 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STB80NE03L-06 / STB80NE03L-06-1 D2PAK MECHANICAL DATA mm. DIM. MIN. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 0 4.88 15 1.27 1.4 2.4 0.4 8 10 8.5 5.28 15.85 1.4 1.75 3.2 0.192 0.590 0.050 0.055 0.094 0.015 4.4 2.49 0.03 0.7 1.14 0.45 1.23 8.95 8 10.4 0.393 0.334 0.208 0.625 0.055 0.068 0.126 TYP MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 MIN. 0.173 0.098 0.001 0.027 0.044 0.017 0.048 0.352 0.315 TYP. MAX. 0.181 0.106 0.009 0.036 0.067 0.023 0.053 0.368 inch 3 7/9 1 STB80NE03L-06 / STB80NE03L-06-1 TO-262 (I2PAK) MECHANICAL DATA mm MIN. A A1 B B2 C C2 D e E L L1 L2 4.4 2.49 0.7 1.14 0.45 1.23 8.95 2.4 10 13.1 3.48 1.27 TYP. MAX. 4.6 2.69 0.93 1.7 0.6 1.36 9.35 2.7 10.4 13.6 3.78 1.4 MIN. 0.173 0.098 0.027 0.044 0.017 0.048 0.352 0.094 0.393 0.515 0.137 0.050 inch TYP. MAX. 0.181 0.106 0.036 0.067 0.023 0.053 0.368 0.106 0.409 0.531 0.149 0.055 DIM. A C2 B2 B E L1 L2 D L P011P5/E 8/9 e A1 C STB80NE03L-06 / STB80NE03L-06-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 9/9 |
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